EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

These design guidelines provide the best practices for DDR and DDR2 SDRAM custom memory interface implementation in Stratix III and Stratix IV FPGAs. Figure 1 shows the design flow that is required ...
EDN

JEDEC begins to draft standard for advanced DDR-III SDRAM chips

Future-generation DDR-III SDRAM surfaced here last week at the JEDEX chip conference, flaunting performance levels twice as good as DDR-II. The JEDEC Solid State Technology Association, the ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
TechRepublic

Implementation of DDR SDRAM Controller Using Verilog HDL

Now-a-days, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has become the most popular class of memory used in computers due to its high speed, burst access and pipeline feature ...
ZDNet

Samsung bets on memory standard

Samsung has begun shipping engineering samples of 200MHz double-data-rate (DDR) SDRAM memory, or DDR400, in spite of doubts over whether the PC infrastructure industry will ever widely adopt the ...
Semiconductor Engineering

DDR5: How Faster Memory Speeds Shape The Future

Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the ...
ExtremeTech

Micron's 320GB/sec Hybrid Memory Cube comes to market in 2013, threatens to finally kill DDR SDRAM

The Hybrid Memory Cube Consortium, which consists of such silicon luminaries as Micron, Samsung, and IBM (but not Intel), has finally finished hammering out the Hybrid Memory Cube 1.0 standard. The ...
CNET

FTC sets limits on Rambus royalties

The Federal Trade Commission in a decision announced Monday substantially limited the size of royalties that memory chipmaker Rambus can charge for its DRAM technology. The commission's order sets a ...
Digi Times

Powerchip successful on 256Mbit DDR SDRAM pilot run

Powerchip Semiconductor on March 1 announced the successful pilot production of 256Mbit, 0.18-micron configuration DDR SDRAM memory. The sample product has been sent for certification and volume ...
Electronic Design

The Vanishing Data Valid Window

There are many parameters, both electrical and physical, that contribute to the relative size of tDV and not all scale with operating speed. Factors such as signal noise, crosstalk, skew, jitter, and ...
Ars Technica

Memory refresh rate is < better or > ?

I am running two different dimms and was wondering about thier refresh rates.<BR>Here is a reference to what I am talking about<BR><BR>Memory Module Properties <BR>Module Name Smart Modular ...