EDN

Clocking chips simplify system design with low additive jitter

Santa Clara, Calif. — National Semiconductor Corp. has introduced a family of three ultra-low-noise and fully-featured clock buffers, dividers and distributors that simplify system clock design while ...
EDN

Challenges of clocking a high-definition world, (Part 2 of 2): A system applications perspective

Part 1 of this two-part series (click here) covered the fundamental aspects of jitter relative to clocking an ADC and the impact of jitter on the sampled signal. It derived the fundamental expression ...
Electronic Design

Programmable Clock Generator Solves System-Timing Woes

Flexible clock chip tackles design and timing issues by integrating 2 kbits of in-system-programmable EEPROM and 16 kbits of extra EEPROM storage. Timing within all digital and most mixed ...
Electronic Design

Multiservice Router Clock Circuit Design Challenges

What’s a multiservice router/ switch? Multiservice routers and switches are network devices that support multiple switching and routing protocols, typically adding Multiprotocol Label Switching (MPLS) ...